SHAPES: Four HW and SW Research positions at INFN Roma in 2006 APE Massive Parallel Processor Design Group of INFN Roma, Italy opens 4 positions and invites applications for the following research areas: HW/SW Architecture - Architecture Description Languages and generation of programming environments and hardware description for communication aware VLIW processors. HW System Engineering - Methodologies for high-density 3D toroidal massive parallel processors/embedded systems. HW design - HW Intellectual Properties (IPs) for inter-processor communication and numerical computations. SW Design - Programming Environments and Operating Systems for Massive Parallel Processors/Embedded Systems. These four positions are funded by the European Integrated Project SHAPES: Scalable Software Hardware Application Platform for Embedded System (see project description below). Since 1984, the INFN APE group designed and developed several generations of Massive Parallel Processors for numerical computations. The candidates will work in the INFN APE Labs at the Department of Physics of the University of Roma "La Sapienza", in strict co-operation with the leading institutions participating to the international SHAPES consortium. The initial duration is 2 years, starting in 2006, extendible for additional 18 months. The salary will be commensurate to the experience. Applications should be submitted by January 30th, 2006. Please send CV to piero.vicini@roma1.infn.it and pier.paolucci@roma1.infn.it. SHAPES: Scalable Software Hardware Architecture Platform for Embedded Systems There is no processing power ceiling for the demand of low consumption, low cost, dense DSP for future embedded audio, video, human-centric applications. Nanoscale systems on chip will integrate billion-gate designs. The challenge is to find a scalable HW/SW design style for future CMOS technologies. The main problem is wiring, which threats Moore's law. Future computing architectures for Embedded DSP and Control are strategic and deserve adequate research efforts. Tiled architectures suggest a possible HW path: "small" processing tiles connected by "short wires". Tiled Architectures will cover a significant share of 10+ year embedded applications. SHAPES will set a new density record with multi-Teraops single-board computers and multi-Petaops systems, and will be based on a groundbreaking HW/SW architecture paradigm. The heterogeneous SHAPES tile is composed of a VLIW floating-point DSP, a RISC, on chip memory, and a network interface. It includes a few million gates, for optimal balance among parallelism, local memory, and IP reuse on future technologies. The SHAPES routing fabric connects on-chip and off-chip tiles, weaving a distributed packet switching network. 3D next-neighbours toroidal engineering methodologies will be used for off-chip networking and maximum system density. The SW challenge is to provide a simple and efficient programming environment. SHAPES will investigate a layered system software, which does not destroy algorithmic and distribution info provided by the programmer and is fully aware of the HW paradigm. For efficiency and QoS, the system SW manages intra-tile and inter-tile latencies, bandwidths, computing resources, using static and dynamic profiling. The SW accesses the on-chip and off-chip networks through a homogeneous interface. The same HW and SW interface is adopted for integration with signal acquisition and reconfigurable logic tiles. Hereafter the members and main roles of the partners of the SHAPES consortium: ATMEL Roma (co-ordinating partner) Processing Tile. ETH Zurich Distributed Operation Layer. RWTH Aachen University Simulation of Multi Processor Systems. TIMA Grenoble Laboratory and THALES Hardware Dependent Software Layer and OS. TARGET Compiler Technologies Retargetable VLIW Compilers. STMicroelectonics with Universities of Cagliari and Pisa Packet Switching NoCs. INFN Roma 3D Dense System/Processor Eng. Methodology. FRAUNHOFER IDMT&IGD Digital Multimedia and Computer Graphics. PIE and MEDCOM Ultrasound Scanners dott. Pier Stanislao Paolucci - SHAPES Coordinator Technology Director ATMEL Roma Advanced DSP Via V.G. GALATI, 87 - 00155 Roma - Italy mobile phone: +39 329 63 15 069 - Tel: +39 06 40 90 14 21 - Fax: +39 06 40 50 16 13 pier.paolucci@atmelroma.it http://www.atmelroma.it Permanent Staff Researcher (part time) Istituto Nazionale di Fisica Nucleare - Roma Dip. di Fisica - Univ. Roma "La Sapienza" phone: +39 06 49 91 45 07 pier.paolucci@roma1.infn.it